The present invention relates to semiconductor devices used as insulated gate switching devices.
Thyristors have been used as indispensable devices for large capacity power switching owing to the low ON-state voltage characteristic. Gate Turn-Off (GTO) thyristors, for example, are widely used in these days in high-voltage large-current range applications. The GTO thyristor, however, has revealed drawbacks as follows: (1) large gate current is required for turning off the device, and (2) a large-sized snubber is needed to safely turn off the GTO thyristor. In addition, since the GTO thyristor does not show current saturation in its current-voltage characteristic, a passive component, such as a fuse, must be coupled to the thyristor so as to protect a load from short-circuiting. This greatly impedes the reduction in the size and cost of the whole system.
In 1984, MOS controlled thyristor (hereinafter abbreviated to MCT) as a voltage-driven type thyristor was proposed by Temple et al. of General Electric in IEEE IEDM Tech. Dig., pp.282 (1984). Since then, the characteristics of this type of thyristor have been analyzed and improved in various institutions worldwide. This is because the MCT, which is a voltage-drive type device, requires a far simpler gate circuit than the GTO thyristor, while assuring a relatively low ON-state voltage characteristic. The MCT, however, does not show a current saturation characteristic as in the case of the GTO thyristor, and therefore requires a passive component, such as a fuse, in practical use.
In the meantime, U.S. Pat. Nos. 4,847,671 and 4,502,070 disclose semiconductor devices having current saturation characteristics, wherein a thyristor is connected in series with MOSFET. These known devices, however, show effective saturation characteristics only where a low voltage is applied thereto, and may break down if a voltage that is equal to or higher than the breakdown voltage of the MOSFET connected in series is applied to the anode. To solve this problem, M. S. Sheker and others disclosed a dual channel type emitter switched thyristor (EST) in IEEE Electron Device Letters, vol. 12, pp.387 (1991), and proved through actual measurements that this type of device shows a current saturation characteristic even in a high voltage range. Subsequently, Iwamuro et al. presented results of their analysis on a forward bias safe operation area (FBSOA) and a reverse bias safe operation area (RBSOA) of the EST in ISPSD ""93, pp.71, (1993) and ISPD ""94, pp195 (1994), and paved the way to the development of voltage-driven type thyristors having safe operation areas in which the device operates safely when a load is short-circuited. Device structures similar to the EST are also disclosed in U.S. Pat. Nos. 5,381,026 and 5,464,994.
Kitagawa et al. disclosed in laid-open Japanese Patent Publication (Kokai) No. 7-50405 IEGT (Injection Enhanced Gate Transistor) that employs a gate trench structure in a voltage-driven type transistor structure, so as to achieve carrier distribution that is close to that which appears in the operation of thyristors. While the basic operation of this device is exactly the same as that of IGBT (Insulated Gate Bipolar Transistor), a portion of the surface of the device through which current passes is given a smaller area than that of IGBT, so as to raise the resistance and vary the carrier distribution inside the device to a greater extent, in particular, increase the carrier concentration at the surface of the device. To this end, the width of the trench portion may be made greater than that of the mesa portion. In the actual fabrication of such a device that has a large trench width, however, it is difficult to uniformly embed polysilicon in the inside of the trench, or the shape of the trench is undesirably changed. Thus, the current manufacturing level only permits formation of a trench having a width up to about 1.5 xcexcm. To solve this problem, Kitagawa et al. proposed in ISPSD ""95, pp.486 (1995) a device having narrow trench gate electrodes and p regions held in a floating state in terms of the potential, which are formed alternately, so as to provide the same effect as provided by the device having a large trench width. Similar devices are also disclosed by Kitagawa et al. in ISPSD ""95, pp. 486 (1995), S. Eicher et al. in ISPSD ""98, pp. 39 (1998), and Ogawa et al. in ISPSD ""98, pp. 47 (1998).
The above-described devices are characterized by employing the thyristor structure or trench structure so that the carrier concentration is raised or increased only at the surface of the device, thereby to lower the resistance upon turn-on of the device. Upon turn-off, the carrier distribution of its portion where a depletion layer has spread out is not varied, so that the turn-off loss is reduced, thus enabling the device to achieve a high-speed characteristic equivalent to that of IGBT. Thus, the known devices attempt to lower the ON-state voltage than that of the IGBT, while achieving substantially the same turn-off speed. During the turn-off operation before the depletion layer spread out, however, the carrier concentration is high at the surface of the device as in the ON duration, and the portion of the surface of the device through which current passes is reduced, which results in a slow rate at which a large quantity of carriers present at the surface of the device are drawn away. Accordingly, the turn-off storage time is increased. In view of this situation, Kitagawa et al. proposed a trench IEGT as disclosed in laid-open Patent Publication (Kokai) No. 7-135309, wherein a hole is provided for allowing carriers to be drawn away from a p region that is in a floating state in terms of the potential, through MOSFET, so that the switching speed is increased. The structure of the trench IEGT as disclosed in laid-open Patent Publication 7-135309 will be now described in detail.
FIG. 7 is a perspective view showing cross sections of a principal part of the trench IGBT as one type of known device. In the device of FIG. 7, a first p base region 74 and a second p base region 75 are formed in a surface layer of an n base region 73, and a plurality of n source regions 76 are formed in a surface layer of the first p base region 74 such that the regions 76 are spaced apart from each other. A trench is formed which extends from the surface of the device to a certain depth, and a gate electrode 78 is formed in the trench with a gate insulating film 77 interposed between the gate electrode 78 and the inner wall of the trench.
A cathode electrode 82 is formed on the surface of the first p base region 74 and the n source regions 76. The second p base region 75 extends continuously in the Z-axis direction, until one end of the region 75 reaches an n base region 87 as part of the n base region 73. Also, a p+region 88 is formed outwardly of the n base region 87. The p+region 88 is connected to the first p base region 74. It is to be understood that the n base region 87 is a portion of the n base region 73 that is interposed between the second p base region 75 and the p+region 88.
The trench extends in the Z-axis direction until it reaches the p+region 88, and the cathode electrode 82 is formed on the surface of the p+region 88. A p emitter region 71 is formed on the rear surface of the n base region 73, and an anode electrode 83 is formed on the surface of the p emitter region 71. The anode electrode 83, cathode electrode 82, and the gate electrode 78 are connected to an anode terminal A, cathode terminal K and a gate terminal G, respectively. It is to be noted that the n source region 76, p emitter region 71, cathode electrode 82, anode electrode 83, cathode terminal K and the anode terminal A respectively correspond to an n emitter region, p collector region, emitter electrode E, collector electrode C, emitter terminal E and a collector terminal C, which will be described later in preferred embodiments of the present invention. In the trench IEGT as disclosed in laid-open Japanese Patent Publication (Kokai) No. 7-135309, n source regions 76 and p+regions are formed alternately in the surface layer of the first p base region 74, and a p+region is formed in the surface layer of the second p base region 75. In the trench IEGT shown in FIG. 7, on the other hand, the first p base region 74 and second p base region 75 are to be considered as incorporating these p+regions. While the first p base region is formed as a lower layer of the p+region 88 in the EGT disclosed in the above-identified publication, the p+region 88 as shown in FIG. 7 is regarded as incorporating the first p base region.
In the above trench IEGT, the gate electrodes 78 having a narrow trench structure and the second base regions 75 that are in a floating state in terms of the potential are formed alternately in the X-axis direction, so that the area of a surface portion through which current passes is reduced as compared with that of the IGBT, whereby the carrier distribution inside the device varies to a great extent, namely, the carrier concentration at the surface of the device is increased, with a result of reduced resistance upon turn-on of the device. Upon turn-off, the carrier distribution is not varied after a depletion layer spreads out, so that the turn-off loss and turn-off time are reduced, and the IEGT achieves a high-speed switching characteristic equivalent to that of the IGBT.
During a turn-off operation of the above trench IGBT before the depletion layer spreads out, however, the carrier concentration at the device surface is relatively high as is during turn-on, and the current passes through a relatively small area of the surface portion (that corresponds to the area of contact holes). Furthermore, carriers present in the second p base region 75 and the p+region 88 formed in the surface layer of the second p base region 75 flow into the first p base region 74 and the p+region 88, only through a p channel 90 formed in the n base region 73 at the bottom and part of side faces of the trench, and a p channel 89 formed in the n base region 87 along side walls of the trench located at the opposite ends of the second p base region 75 as viewed in the Z-axis direction (only one of the opposite ends is illustrated in FIG. 7).
The p channel 90 as described above has a relatively large channel length, namely, provides a long current path. While the p channel 89 formed along the side wall of the trench has a small channel length, the carriers that have been accumulated in the second p base region 75 formed continuously in the Z-axis direction must be drawn away through the p channels 89 at the opposite ends of the region 75, resulting in an increased density of carriers flowing through the channel.
As described above, carriers must be drawn away through a long channel (90) formed at the bottom portion of the trench. Alternatively, carriers must be drawn away through a channel (89) formed along the side wall of the trench, with a high carrier density. Thus, it takes time to draw away a large quantity of carriers present at the device surface, irrespective of which path or channel is used for drawing away the carriers, resulting in an increase in the turn-off storage time. Also, the p+region 88 needs to be provided for allowing carriers to be drawn away, but current does not flow through the p+region 88 while the device is in the ON state. Thus, the p+region 88 provides useless space upon turn-on, and therefore the ON-state voltage (ON resistance) of the device is increased.
It is an object of the present invention to provide a semiconductor device that assures both low ON resistance and high-speed turn-off characteristic, and also has a switching characteristic with a short turn-off storage time.
To accomplish the above object, the present invention provides a semiconductor device, comprising: a first-conductivity-type first base region; a gate electrode formed on a gate insulating film within a groove that is formed in a selected elongate portion of a surface layer of the first base region; a second-conductivity-type second base region formed in a selected portion of the surface layer of the first base region, such that the second base region has a smaller depth than the groove, and is located adjacent to the groove; a source region formed in a selected portion of a surface layer of the second base region, to be located adjacent to the groove; a second-conductivity-type third base region that is formed in a selected portion of the surface layer of the first base region, apart from the second base region, to be located adjacent to the groove; a first main electrode formed in contact with the source region and the second base region; a collector region formed in a rear surface layer of the first base region; and a second main electrode formed on the collector region, wherein the second base region and the third base region are alternately formed on at least one of side faces of the groove in a longitudinal direction of the groove.
In one preferred form of the invention, the second base region and the third base region are formed on the opposite sides of the groove as viewed in the longitudinal direction thereof
In another preferred form of the invention, the second base region and the third base region are opposed to each other with the groove located therebetween.
In the semiconductor device of the present invention as described above, the second base region is located adjacent to the third base region that is in a floating state in terms of the potential, and the two base regions, i.e., the second and third base regions, cooperate with the gate insulating film and the gate electrode to constitute a gate electrode portion. In operation, an inversion layer is formed in the first base region right under the gate electrode, so that the second base region and the third base region are connected with each other and have the same potential. In this state, carriers accumulated in the vicinity of the surface of the device flow through the inversion layer from the third base region, to be drawn away through the second base region, so that the device can be immediately turned off. Further, the second base region and the third base region are formed alternately in the longitudinal direction of the device with certain spacing therebetween, so that carriers are also drawn away in the longitudinal direction through an inversion layer formed at the interface of the first base region located along a side wall of the trench gate electrode. Since the second base region also serves as a p+layer for carriers as required in the IEGT proposed by Kitagawa et al., there is no particular need to provide such a p+layer, and the effective area of the chip can be accordingly increased, with a result of an even smaller ON resistance than that of the IEGT.
In a further preferred form of the invention, a first-conductivity-type fourth base region having lower resistance than the first base region is formed between the rear surface of the first base region and the collector region.
With the fourth base region (that is generally called xe2x80x9cbuffer regionxe2x80x9d) thus provided, the thickness of the first base region can be reduced, thus making it easy for the device to provide a higher breakdown voltage. Furthermore, where the device is a 600V-class device with a medium breakdown voltage, the tradeoff between the saturation voltage and the turn-off characteristic can be improved as compared with the case where no buffer region is provided.
It is preferable to drive the semiconductor device of the present invention such that a first-conductivity-type channel is formed in the second base region upon turn-on, and a second-conductivity-type channel is formed in the first base region upon turn-off.
More specifically described, a positive voltage is applied to the gate electrode to turn on the device, so that the first-conductivity-type channel is formed in the second base region, and a negative voltage is applied to the gate electrode to turn off the device, so that the second-conductivity-type channel is formed in the first base region.
Thus, positive or negative voltage is selectively applied to the gate electrode, so as to easily turn on or off the semiconductor device. As described above, the second-conductivity-type channel is formed upon turn-off in the first base region that is in contact with the side wall of the trench, and therefore carriers in the vicinity of the third base region can be efficiently drawn away into the second base region, assuring an improved tradeoff between the saturation voltage and turn-off characteristics.
It may also be possible to drive the semiconductor device by reversing the polarity of the voltage applied to between the gate electrode and the first main electrode upon turn-on and turn-off.